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8
4428E–8051–02/08
AT/TS80C31X2
Figure 6-2.
Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD
mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that
all peripherals using clock frequency as time reference (UART, timers) will have their time refer-
ence divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel-wm.com)
XTAL1:2
XTAL1
CPU clock
X2 bit
X2 Mode
STD Mode
Table 6-1.
CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
X2
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
X2
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
OSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC=FXTAL).
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